module addr_unit_8pt
(
  //OUTPUTS
  output wire [1:0]addr_bank0,          //Address to Memory Bank 0
  output wire  [1:0]addr_bank1,          //Address to Memory Bank 1
  output ready,                               //Last Stages is completed
  output reg exc_sel0,                            //Select Signal for Butterfly exchange 0
  output reg exc_sel1,                            //Select Signal for Butterfly exchange 1
  //INPUTS
  input enable,                               //Enables generation to next address
  //input restart,                              //Restart address generation unit
  input clk,
  input rst_n
);


reg  [3:0] counter;
wire [1:0] stage_cnt;
wire [1:0] butt_cnt;

reg [2:0] sft_reg;

assign stage_cnt = counter[3:2];
assign butt_cnt  = counter[1:0];

assign ready = (stage_cnt == 2'b10 && butt_cnt == 2'b11);

always @(posedge clk, negedge rst_n)
  begin
    if(!rst_n)
      counter <= 4'b1111;
    else
      if(enable)
        counter <= (ready) ? 4'd0 : counter + 1;  
  end
  
  always @(*)
    begin
      case(stage_cnt)
        2'b00:   {exc_sel0, exc_sel1} = {1'b0, butt_cnt[1]};
        2'b01:   {exc_sel0, exc_sel1} = {butt_cnt[1], butt_cnt[0]};
        2'b10:   {exc_sel0, exc_sel1} = {butt_cnt[0], 1'b0};  
        default: {exc_sel0, exc_sel1} = {1'b0, 1'b0};
      endcase
    end
  /*  
  always @(*)
    begin
      case(stage_cnt)
        2'b00:   addr_bank1 = butt_cnt;
        2'b01:   addr_bank1 = {~butt_cnt[1], butt_cnt[0]};
        2'b10:   addr_bank1 = ~butt_cnt;
        default: addr_bank1 = 2'b00;
      endcase
    end
   */ 
  assign addr_bank0 = butt_cnt;
  
  always @(posedge clk, negedge rst_n)
    begin
      if(!rst_n)
        sft_reg <= 2'b00;
      else
        if(enable)
          if(ready)
            sft_reg <= 3'b001;
          else
            if(butt_cnt == 2'b11)
              begin
                sft_reg[2] <= sft_reg[1];
                sft_reg[1] <= sft_reg[0];
                sft_reg[0] <= 1'b1; 
              end    
    end
  
  generate
    genvar i;
    for(i=0; i < 2; i = i + 1)
      assign addr_bank1[i] = (sft_reg[2 - i]) ? ~butt_cnt[i] : butt_cnt[i];   
  endgenerate
  
endmodule
